1. Field of the Invention
The present invention relates to a field effect transistor (FET) that operates in microwave and millimeter-wave region and more particularly to an FET having a two-stage recess structure.
2. Description of the Prior Art
Recently, tertiary and quaternary mixed crystal semiconductors such as InGaAs and InGaAsP have been drawing much attention. Among them, InGaAs lattice matched to an InP substrate is regarded as an especially promising material for not only optical devices but also various kinds of FETs. As a consequence, FETs utilizing a two-dimensional electron gas (2DEG) formed on heterointerfaces of InGaAs with InP or InAlAs have been particularly widely studied.
The reasons why InGaAs, in comparison with GaAs and the like, is considered highly as an electron transport device are as follows: (1) the peak value in electron drift velocities is high, (2) the electron mobilities at low electric fields are high, (3) it is easy to form ohmic contact electrodes and the contact resistances thereof are low, (4) the electron velocity overshoot is expected to take place, (5) noise owing to the valley scattering is low and (6) characteristics of the insulator-semiconductor interfaces are relatively good. And besides, that the afore-mentioned 2DEG device is realizable is one of the main factors.
At present, an FET utilizing a 2DEG system of the InAlAs/InGaAs interface is expected as a potential high quality device for microwave and millimeter-wave application and has been investigated in various aspects. In particular, as a low noise element, effectiveness thereof has been confirmed by experiments. For example, at 94 GHz, noise figure of 1.2 dB and incidental gain of 7.2 dB at room temperature were reported by K. H. Duh et al. in IEEE Microwave and Guided Wave Letters, Vol.1, No.5, P.114-116, 1991. These results were obtained in a device fabricated from a material system lattice matched to an InP substrate. That is, the composition of In in the material system was set as In0.52Al0.48As/In0.53Ga0.47As. In this system, a 2DEG is formed in the In0.53 Ga0.47As layer. In order to improve the device characteristics further, various attempts including the use of different In composition in an InGaAs channel layer, for example, setting higher than 0.53, as reported by G. I. Ng et al. in IEEE Electron Device Letters, Vol.10, No.3, P.114-116, 1989, have been made.
In such an InAlAs/InGaAs heterojunction FET, InGaAs is, in general, widely utilized as a 2DEG channel, of which the band gap is around 0.75 eV and smaller than that of GaAs and hence the rate of impact ionization is higher. Therefore, the breakdown voltage for a device is small in comparison with that for a GaAs heterojunction FET. For a stable device performance, the device is required to have a higher breakdown voltage and, in order to achieve this, several approaches have been made; on the one hand, new designs for the epilayer of the device, and on the other hand, the optimization of geometry around the gate, for example, through an expansion of the gate recess, has been investigated.
Further, in case that a high density cap layer is used, by setting the recess edge of this cap layer as far from the gate electrode as possible, an electric field generated by the applied voltage through the gate can be alleviated, which results in the lower rate of impact ionization of channel electrons. This also contributes to the reduction of the parasitic capacitance between the gate and cap layer, leading to an increase in the power gain of the device. On the side of the source electrode, however, this causes an increase in the source resistance and therefore is counterbalanced by the degradation of characteristics.
Generally, InAlAs semiconductors have a problem of surface instability, resulting from surface oxidation and the like. On the recess surface around the gate, electron traps to capture electrons sometimes develop, depending on the semiconductor material. In aforementioned InAlAs/InGaAs heterojunction FETs, InAlAs is often utilized as a Schottky layer of gate electrode, but this InAlAs lattice matched to an InP substrate contains nearly 50% of Al so that the surface trap density due to oxidation and the like is high, often causing a problem of surface instability.
A two-stage recess structure is a known method to stop reflecting the surface instability on the device characteristics. This structure is fabricated by etching a cap layer to form a relatively wide recess, and forming, within this first recess, a second recess with a narrower recess width, and then forming a gate within this narrower second recess. The surface of the Schottky semiconductor by the side of the gate is, in this structure, placed higher than the position at which the gate electrode is formed. In this manner, even when surface instability resulting from electron traps on the semiconductor surface and the like exists, the device performance is not affected.
FIG. 14 shows one example of conventional two-stage recess structures. In this structure, upon a semi-insulating InP substrate 201, an undoped InAlAs layer 202 as a buffer layer, an undoped InGaAs layer 203 as a channel layer, an undoped InAlAs layer 204 and an n-type doped InAlAs layer 205 as electron supply layers which supply carriers to the channel layer (an undoped InAlAs layer 204 may be regarded as a spacer layer), an undoped InAlAs layer 206 as a Schottky layer, and an n-type doped InGaAs layer 207 as a cap layer to have electrical contacts with electrodes, are grown in succession, and further, a first recess 209 is set through the cap layer (the n-type doped InGaAs layer 207) and then a second recess 210 is set within this first recess by removing a part of Schottky layer. On the exposed surface of the Schottky layer at the bottom of this second recess opening, a gate electrode 208a is formed and on the cap layer (the n-type doped InGaAs layer 207) a source electrode and a drain electrode are formed.
In such a conventional structure, if the source electrode and the drain electrode are made of metal materials and form non-alloy ohmic contacts without metal materials being alloyed with semiconductor layers, a discontinuity of the conduction-bands between InGaAs which is normally used for a cap layer and InAlAs which is normally used for a Schottky layer is large, thus causing a problem of high contact resistance.
As for the conventional FET which is fabricated upon a GaAs substrate, alloy-type ohmic electrodes, for which AuGe and Ni are used to form a source electrode and a drain electrode and then alloyed, are widely utilized in order to lower the contact resistance.
Yet, when alloy-type ohmic electrodes of AuGe and Ni are applied to a heterojunction FET fabricated upon an InP substrate, as pointed out by K. Onda et al. in MTT Symposium Proceedings, P.261-264, 1994, for example, in acceleration tests carried out at around 300xc2x0 C., alloying progresses further and the resistance increases. Therefore, a problem of unreliability may arise in actual practical situations.
Meanwhile, in IEEE Electron Device Letters, Vol.13, P.325, 1992, it is demonstrated that, in a heterojunction FET having a single recess structure, non-alloy ohmic contacts can be formed by growing, upon an undoped InAlAs Schottky layer, cap layers which consist of an n-type InAlAs layer and an n-type InGaAs layer, overlying in succession. Nevertheless, in a two-stage recess structure using an InP substrate, non-alloy ohmic contact has not been known yet.
Further, with respect to this epi-structure, when the usual manufacturing method is applied to the two-stage recess structure, a first recess is formed through to an undoped InAlAs Schottky layer, and a second recess, with a narrower width than the first recess, is formed within the wider first recess, and then a gate electrode is formed within the narrower second recess. But, in this structure, at the time of the formation of the first recess, two overlying cap layers of InGaAs and InAlAs are to be simultaneously removed, and thereby causes the problem of an increase in sheet resistance right under the first recess. Further, an undoped InAlAs Schottky layer is exposed at the bottom of the first recess so that the potential profile changes gradually from this exposed surface to the interior, which leads to another problem that the influence of the surface tends to appear on the device operation.
Further, as a method of manufacturing of a two-stage recess-type FET, it was a general practice that, a first recess with a wide opening is formed at the first stage by etching, and then a second recess with a narrower opening than the first is formed within the first recess by another etching. In this method, however, steps of exposure using photoresist, developing and etching are each required twice, which makes steps of manufacturing process rather complicated.
In light of the above problems, an object of the present invention is to provide an FET, having a two-stage recess structure formed upon an InP substrate and showing stable device characteristics, and particularly a stable FET with a low contact resistance.
A further object of the present invention is to provide a method of manufacturing such a high performance two-stage recess-type FET under good control.
The present invention is directed to an FET, comprising, upon an InP substrate;
a channel layer formed from an undoped semiconductor,
an electron supply layer in which n-type impurities are doped partially or all along the direction of the thickness, for supplying carriers to said channel layer,
an undoped InAlAs Schottky layer,
an n-type InAlAs first cap layer set in contact with said Schottky layer,
an n-type InGaAs second cap layer set in contact with said first cap layer,
a first recess opening bored through said second cap layer,
a second recess opening which is bored, within the first recess opening, through said first cap layer till just the surface of said Schottky layer is reached, or the interior of said Schottky layer by removing a part thereof.
a gate electrode formed on the exposed surface of said Schottky layer at the bottom of the second recess opening, and
a source electrode and a drain electrode which are formed upon said second cap layer on each side of said first recess opening.
This FET may be manufactured by a method comprising steps of:
forming a channel layer of an undoped semiconductor upon an InP substrate,
forming an electron supply layer in which n-type impurities are doped partially or all along the direction of the thickness for supplying carriers to said channel layer,
forming an undoped InAlAs Schottky layer,
forming an n-type InAlAs first cap layer over the entire surface of said Schottky layer,
forming an n-type InGaAs second cap layer over the entire surface of said first cap layer,
forming a first recess opening into a prescribed shape by etching from the surface of the second cap layer through the second and the first cap layers to just the surface of said Schottky layer or further to a level to remove a part of said Schottky layer, and
forming, in succession, a second recess opening, relatively wider than said first recess opening, into a prescribed shape by side-etching the second cap layer using an etchant of which the etching selectivity of InGaAs over InAlAs is 30 or more.
A similar method can be applied to manufacturing an FET in conventional structure. Namely, this manufacturing method comprises the steps of:
forming a channel layer from an undoped semiconductor upon an InP substrate,
forming an electron supply layer in which n-type impurities are doped partially or all along the direction of the thickness for supplying carriers to said channel layer,
forming an undoped InAlAs Schottky layer,
forming an n-type InGaAs cap layer over the entire surface of said Schottky layer,
forming a first recess opening into a prescribed shape by etching from the surface of the said n-type InGaAs cap layer through said n-type InGaAs cap layer to a level to remove a part of said Schottky layer, and
forming, in succession, a second recess opening, relatively wider than said first recess opening, into a prescribed shape by side-etching said n-type InGaAs cap layer, using an etchant of which the etching selectivity of InGaAs over InAlAs is 30 or more.
In the present invention, because the use of the n-type InAlAs first cap layer reduces the resistances between the n-type InGaAs second cap layer and the undoped InAlAs Schottky layer, low contact resistance is obtained even using non-alloy ohmic electrodes.
Further, the bottom of the first recess is on the n-type InAlAs first cap layer. The profile of the second recess shows a steep angle in the n-type InAlAs first cap layer, and becomes almost horizontal in the undoped InAlAs Schottky layer. That is to say, the interior of the device is not easily affected by the condition of the surface, and, therefore, the device of particularly stable performance is easily obtained.
In the FET, according to the present invention, gate recess is in the form of two stages and the gate-semiconductor contact is placed in the sections etched deeper than the semiconductor surface neighboring the gate side so that variations in device characteristics owing to instability of the semiconductor surface is well suppressed.
Further, in the manufacturing method according to the present invention, the n-type InGaAs second cap layers which is the outermost surface layers, is etched selectively after the gate contact face is exposed, and, hence, the second recess opening can be formed with excellent controllability. At the same time, manufacturing steps are simplified and the manufacturing cost is reduced.
In addition, a similar manufacturing method to this can be applied to the conventional device structure in which an n-type InAlAs layer is not utilized as a layer of the cap layers right under the InGaAs outermost surface layer.